Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

By Pierluigi Nuzzo, F. Bernardinis, P. Terreni, G. V. D. Plas. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2008

342 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/dbb43cba4d0ffce46fd6f8a37291fee6ec3e07cb

How researchers see this paper

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In Biomedical Engineering

1. Reza Lotfi
2. Samaneh Babayan Mashhadi

In Electrical and Electronic Engineering

1. Reza Lotfi
2. Samaneh Babayan Mashhadi

Citations in the corpus

• Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator (2014, methodology): “Since the comparator offset [11] can be reduced by using known techniques [3], the main focus of this paper is the comparator speed and power dissipation.”
• A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS (2013, background): “It is assumed that each constants ( ) for a settling error 0.5 LSB. unit capacitor has its own buffer and that therefore the driver strength is proportional to the switched capacitance.”