Robust Boolean reasoning for equivalence checking and functional property verification

By A. Kuehlmann, Viresh Paruthi, F. Krohm, Malay K. Ganai. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

351 citations recorded by the source corpus.

Subfields: Computational Theory and Mathematics, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/d680df94a105ca238d97ef6aa7f70e2e5e47bda1

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computational Theory and Mathematics

1. Armin Biere
2. Alan Mishchenko
3. Robert K. Brayton
4. Niklas Eén
5. Frank Hutter
6. Torsten Schaub
7. Martin Gebser
8. Benjamin Kaufmann

In Electrical and Electronic Engineering

1. Alan Mishchenko
2. Robert K. Brayton
3. Armin Biere
4. Niklas Eén
5. Armando Solar-Lezama
6. Rastislav Bodík

In Hardware and Architecture

1. Alan Mishchenko
2. Robert K. Brayton
3. Armin Biere
4. Niklas Eén
5. Armando Solar-Lezama
6. Rastislav Bodík

Citations in the corpus

• ABC: An Academic Industrial-Strength Verification Tool (2010, methodology): “To this end, a combinational miter is constructed and solved using a set of integrated methods, including simulation, SAT solving, and BDD or SAT sweeping [22].”
• Effective Preprocessing in SAT Through Variable and Clause Elimination (2005, methodology): “Other similar techniques have been used in the context of ATPG, such as recursive learning [8], or in circuit verification, in particular andinverter graphs [9] and BDD-sweeping [9].”