In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array
By Jintao Zhang, Zhuo Wang, Naveen Verma. IEEE Journal of Solid-State Circuits, 2017
436 citations recorded by the source corpus.
Subfields: Computational Theory and Mathematics, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/d1b53e3a977dffe016d88387e59e48d6dbdedcc6
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computational Theory and Mathematics
In Electrical and Electronic Engineering
- Anantha P. Chandrakasan
- Avishek Biswas
- Naveen Verma
- Massimo Alioto
- Mohamed F. Younis
- Xuxun Liu
- Deborah Estrin
- Ian F. Akyildiz
Citations in the corpus
- CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks (2019, methodology): “signals have less variations typically, compared to those arising from local Vt mismatch in the pMOS devices [13].”
- In-Memory Computing: Advances and prospects (2019, methodology): “Consider accessing D bits of data from a D D # memory [7]: ■ Bandwidth: In the conventional architecture, bandwidth scales as D / 1 2 with the number of row-wise access cycles required.”