Dynamic power consumption in Virtex™-II FPGA family

By L. Shang, A. Kaviani, Kusuma Bathala. Symposium on Field Programmable Gate Arrays, 2002

454 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/c0c4bcf7ebeae81fe610c16ff7c711371846850f

Citations in the corpus

• Measuring the Gap Between FPGAs and ASICs (2006, background): “Past studies have estimated that I/O power consumption is approximately 7%–14% of the total dynamic power consumption [31], [32], but this can be very design dependent.”