Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

By Ning Zhu, W. Goh, Weija Zhang, Kiat Seng Yeo, Zhi-Hui Kong. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2010

374 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b9f6f5c899cc3b76e0c3d6f45d337f9a8c883eff

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In Electrical and Electronic Engineering

1. Kiat Seng Yeo
2. G. Wang

Citations in the corpus

• Enhanced low-power high-speed adder for error-tolerant application (2009, methodology): “In our previous design, ETAI [ 7 ], the power and speed performances are also commendable.”