An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists

By áTå iÞéÍÞÕåã¢Ù1åèÄä, ÜcÝ¢éÅã¢æÕêßéÄß ãHæiåWã, ã¢æiÙÚBáTå 5ðqÙ3ÙáéÅÙ, cãHèÅÚéÄêmâÕèÄÙêmÙ oã¢ÙzÞ5é. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2001

313 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition

View Paper: https://www.semanticscholar.org/paper/a87cea658f8fc17416688532078f1468edc1d94d

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Artificial Intelligence

1. Kris Gaj
2. Pawel Chodowiec

In Computer Vision and Pattern Recognition

1. Kris Gaj
2. Pawel Chodowiec

Citations in the corpus

• Very Compact FPGA Implementation of the AES Algorithm (2003, methodology): “We also collected information about other existing architectures capable of encrypting or decrypting data in feedback modes of operation [15] [16] [17] [24] [26].”