A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

By M. Le Gallo, R. Khaddam-Aljameh, M. Stanisavljevic, A. Vasilopoulos, B. Kersting, M. Dazzi, Geethan Karunaratne, M. Braendli, Abhairaj Singh, S. Mueller and 20 more. Nature Electronics, 2022

314 citations recorded by the source corpus.

A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference. Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/e28c05440f28c2092a251cf413f2a9d3c90fd1bb

Citations in the corpus

• Neuromorphic computing at scale (2025, unknown): “However, the full potential of these devices in large-scale systems is only beginning to be fully exploited 156 owing to several challenges, such as device non-idealities, challenges in integration with CMOS, and leakage.”