The FEI3 readout chip for the ATLAS pixel detector
By I. Perić, L. Blanquart, G. Comes, P. Denes, K. Einsweiler, P. Fischer, Emanuele Mandelli, G. Meddeler. 2006
248 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Nuclear and High Energy Physics
View Paper: https://www.semanticscholar.org/paper/97efe152e32ea4c0e49ca11f6dc9fbd20bd85df8
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In Electrical and Electronic Engineering
In Nuclear and High Energy Physics
- Atlas Collaboration
- Cms Collaboration
- A. Boveia
- J. Butterworth
- Kyle Cranmer
- J. A. Aguilar-Saavedra
- A. Cooper-Sarkar
- L. Asquith
Citations in the corpus
- The ATLAS Inner Detector commissioning and calibration (2010, methodology): “Due to the finite electronics rise-time, low-amplitude pulses may be assigned to a BC later than the one in which the signal is generated [4].”
- A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology ☆ (2007, methodology): “The same technique has been used in the ATLAS pixel-chip [ 5 ].”
- The ATLAS Experiment at the CERN Large Hadron Collider (2008, methodology): “Sixteen ASIC’s are bump-bonded to each sensor (module).”