RF-CMOS Performance Trends

By P. Woerlee, M. J. Knitel, R. V. Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Z. Duijnhoven. European Solid-State Device Research Conference, 2000

346 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/89d487c3307af98ec48adea892897e46fa87acd0

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In Electrical and Electronic Engineering

1. Ali M. Niknejad
2. Heng Zhang
3. Edgar Sanchez-Sinencio
4. I. Bahl

Citations in the corpus

• Noise modeling for RF CMOS circuit simulation (2003, background): “Both minimum and 50- noise figures will even become better in future CMOS technologies (see [45]).”
• Analog circuits in ultra-deep-submicron CMOS (2005, neutral): “generations [31], [32].”
• A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation (2007, background): “While the noise and bandwidth of nanoscale CMOS improve with scaling, unfortunately the linearity deteriorates with supply voltage and high-field mobility effects [12], [13].”
• An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design (2012, background): “transconductance coefficients, the device figures of merit (FOMs) VIP2 and VIP3 [3], the third-order intercept point (IIP3), and the third-order intermodulation distortion (IMD3)”