A filtering technique to lower LC oscillator phase noise

By Emad Hegazi, Henrik Sjöland, Asad A. Abidi. IEEE J. Solid State Circuits, 2001

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RF-SoC-expectations and required conditions (2002, neutral): “NMOS LNA [4]–[9] and single-sideband (SSB) phase noise for VCO of silicon devices [10]–[24] in the 1–2-GHz frequency range.”
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise (2008, background): “other hand, after [39], the same capacitance has been eschewed by almost all oscillator designers (one notable exception being [40]) as a major source of phase noise deterioration.”
Analysis and design of a 1.8-GHz CMOS LC quadrature VCO (2002, methodology): “The noise filter technique described in [28] has been used in a second design of the same basic S-QVCO, since according to simulations this should afford a phase noise reduction between 2 and 3 dB across the tuning range.”
SiGe bipolar transceiver circuits operating at 60 GHz (2005, background): “The corresponding figure of merit for the VCO [34] is between 181 and 187 dB. Fig.”
All-digital PLL and transmitter for mobile phones (2005, background): “The second resonator operating at 2 of the main resonant frequency providing high-Z [15] improves effective/loaded tank Q.”
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$ (2009, background): “Digital Object Identifier 10.1109/JSSC.2009.2032723 [10] and thus are equally important.”