A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$
By Xiang Gao, Eric A. M. Klumperink, M. Bohsali, Bram Nauta. IEEE Journal of Solid-State Circuits, 2009
354 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/19f876f7d9a2ca639e5b5b9f38fe2666f7371c79
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Citations in the corpus
- Cryo-CMOS Circuits and Systems for Quantum Computing Applications (2018, background): “4This can be easily achieved by employing an integer-N sub-sampling PLL architecture [45] with 50 MHz reference clock (−155 dBc/Hz noise floor).”