Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
By N. Loubet, T. Hook, P. Montanini, C. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, Xin He Miao, J. Wang and 54 more. Symposium on VLSI Technology, 2017
874 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/7f98526a72e7f18ce8a4c98db28d45d51160d58a
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In Electrical and Electronic Engineering
Citations in the corpus
- Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures (2019, methodology): “performance requirements if the proper channel dimension is chosen [38]–[40].”