45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell

By Chia-Pin Lin, Seung-Hyuk Kang, Wang Yu-Jen, K. Lee, X. Zhu, W. Chen, X. Li, W. Hsu, Y. Kao, Monsen Liu and 4 more. International Electron Devices Meeting, 2009

337 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/7a90c32a779ba1df7b441ed7b2f32af48a76eed7

How researchers see this paper

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In Electrical and Electronic Engineering

1. Onur Mutlu
2. Mahmut Taylan Kandemir
3. Anand Sivasubramaniam
4. Emre Kultursay
5. Yoongu Kim

Citations in the corpus

• Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Several prior works have proposed the use of STT technology [29], [35] to reduce energy consumption of the processor and caches [17], [20], [27], [53], [56], [57], [62], [67].”