The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches
By P. Jespers. 2009
172 citations recorded by the source corpus.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/79cb756d57e3e2f10f4558e2a24af39277dcb28a
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In Biomedical Engineering
In Electrical and Electronic Engineering
Citations in the corpus
- Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K (2018, methodology): “It is used to optimize circuits in terms of power, gain, noise and linearity [27]–[29].”