High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding
By Olivier Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, P. Scheiblin, J. Foucher, N. Daval, D. Lafond, L. Tosti and 9 more. 2008 IEEE International Electron Devices Meeting, 2008
177 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/778d5e309159205ade1f48c6bcb50f77f12b503d
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In Electrical and Electronic Engineering
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Citations in the corpus
- Junctionless Transistors: Physics and Properties (2011, background): “Since thin-film SOI wafers with a rTSi \ 0.2 nm can nowadays be produced [ 7 ], threshold voltage variations on the order of rVTH \ 35 mV can be expected at wafer level, provided a lithography width control of 0.5 nm. The use of a thinner EOT decreases the sensitivity of VTH on dimensions.”
- Nanowire transistors without junctions. (2010, methodology): “Simulations indicate a d V TH sd T Si of 80 mV nm −1 in devices with a doping concentration of 1 × 10 19 cm −3 and an EOT of 2 nm, which is approximately twice the variation observed in lightly doped, ultrathin inversion-mode SOI device”