Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors

By J. Tschanz, S. Narendra, Zhanping Chen, Shekhar Y. Borkar, M. Sachdev, V. De. ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581), 2001

328 citations recorded by the source corpus.

Subfields: Computational Theory and Mathematics, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/74895607c66d5af0c57f988c95d010b0afab86e4

Citations in the corpus

• An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008, unknown): “the FPMAC and router logic utilize implicit-pulsed semi-dynamic flip-flops (SDFF) [13], [14].”