Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

By Jason Blocklove, Siddharth Garg, Ramesh Karri, Hammond A. Pearce. Workshop on Machine Learning for CAD, 2023

313 citations recorded by the source corpus.

Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI’s ChatGPT and Google’s Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Given that these ‘conversational’ LLMs perform best when used interactively, we perform a case study where a hardware engineer co-architects a novel 8-bit accumulator-based microprocessor architecture with the LLM according to real-world hardware constraints. We then sent the processor to tapeout in a Skywater 130nm shuttle, meaning that this ‘Chip-Chat’ resulted in what we believe to be the world’s first wholly-AI-written HDL for tapeout.

Subfields: Artificial Intelligence, Computer Networks and Communications, Mechanical Engineering

View Paper: https://www.semanticscholar.org/paper/502bc7694dbe5dbf2bb7aaf576cd2bc13e6b95d8

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Citations in the corpus

VeriGen: A Large Language Model for Verilog Code Generation (2023, background): “In addition, a study conducted by Blocklove et al. [5] showcases the possibility of applying ChatGPT for end-to-end synthesizable hardware design.”
ChipNeMo: Domain-Adapted LLMs for Chip Design (2023, methodology): “Chip-Chat [7] experimented with conversational flows to design and verify a 8-bit accumulator-based microprocessor with GPT-4 and GPT-3.”
VerilogEval: Evaluating Large Language Models for Verilog Code Generation (2023, background): “In the realm of Electronic Design Automation, LLMs provide the potential to aid engineers in designing and verifying digital systems, providing insights into Verilog coding, optimizing circuits, and automating time-consuming tasks [10], [11].”