A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels
By K. Wong, Chi-Ying Tsui, R. Cheng, Wai Ho Mow. IEEE International Symposium on Circuits and Systems proceedings, 2002
420 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Networks and Communications, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/6a170b3abb352613863393f5ce1d321697a7d5da
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Citations in the corpus
- Algorithm and implementation of the K-best sphere decoding for MIMO detection (2006, methodology): “The drawback with the VLSI architecture of [12] is that the decoding throughput is limited to 10 Mb/s at a 100 MHz clock frequency.”
- Fifty Years of MIMO Detection: The Road to Large-Scale MIMOs (2015, background): “There exist a number of other variants of the tree-search based MIMO detectors, which mainly fall into three categories: the depth-first tree-search detector [53], [54], [57]–[61], [80], [82], [319], the breadth-first tree-search detector [62]–[64], [320] and the best-first tree-search detector [68]”
- Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations (2014, background): “tion [13]–[15] or soft-output sphere decoding (SD) [16]–[18],”