A Top-Down method for performance analysis and counters architecture

By A. Yasin. IEEE International Symposium on Performance Analysis of Systems and Software, 2014

359 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/6776ff919597ca4feccd413208dedc401f6e655d

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Parthasarathy Ranganathan
2. David M. Brooks
3. Mark D. Hill
4. Kim M. Hazelwood
5. Ricardo Bianchini
6. Pranith Kumar
7. Lifeng Nai
8. Tipp Moseley

In Electrical and Electronic Engineering

1. Gu-Yeon Wei
2. David M. Brooks
3. Parthasarathy Ranganathan
4. Ricardo Bianchini
5. Pranith Kumar
6. Lifeng Nai
7. Hyesoon Kim
8. Hyojong Kim

In Hardware and Architecture

1. Gu-Yeon Wei
2. David M. Brooks
3. Mark D. Hill
4. Parthasarathy Ranganathan
5. Kim M. Hazelwood
6. Ricardo Bianchini
7. Pranith Kumar
8. Lifeng Nai

Citations in the corpus

• Profiling a warehouse-scale computer (2015, background): “We have observed services that spend virtually all their time paying tax, and would benefit disproportionately from reducing it.”
• GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, methodology): “First, the top graph in Figure 2 shows the execution time breakdown following a top-down methodology described in the Intel manual [22], [23].”
• Pond: CXL-Based Memory Pooling Systems for Cloud Platforms (2022, positive): “Specifically, we use the top-down-method for analysis (TMA) [25, 79].”