Pond: CXL-Based Memory Pooling Systems for Cloud Platforms

By Huaicheng Li, Daniel S. Berger, Stanko Novakovic, Lisa R. Hsu, Dan Ernst, Pantea Zardoshti, Monish Shah, S. Rajadnya, Scott Lee, Ishwar Agarwal and 3 more. International Conference on Architectural Support for Programming Languages and Operating Systems, 2022

468 citations recorded by the source corpus.

Public cloud providers seek to meet stringent performance requirements and low hardware cost. A key driver of performance and cost is main memory. Memory pooling promises to improve DRAM utilization and thereby reduce costs. However, pooling is challenging under cloud performance requirements. This paper proposes Pond, the first memory pooling system that both meets cloud performance goals and significantly reduces DRAM cost. Pond builds on the Compute Express Link (CXL) standard for load/store access to pool memory and two key insights. First, our analysis of cloud production traces shows that pooling across 8-16 sockets is enough to achieve most of the benefits. This enables a small-pool design with low access latency. Second, it is possible to create machine learning models that can accurately predict how much local and pool memory to allocate to a virtual machine (VM) to resemble same-NUMA-node memory performance. Our evaluation with 158 workloads shows that Pond reduces DRAM costs by 7% with performance within 1-5% of same-NUMA-node VM allocations.

Subfields: Computer Networks and Communications, Hardware and Architecture, Information Systems

View Paper: https://www.semanticscholar.org/paper/bf2b5291361e009f7295338f61a0cafac6c54ba7

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Mosharaf Chowdhury
2. Niket Agarwal
3. Abhishek Dhanotia
4. Raouf Boutaba

In Hardware and Architecture

1. Mosharaf Chowdhury
2. Niket Agarwal
3. Abhishek Dhanotia

In Information Systems

1. Mosharaf Chowdhury
2. Abhishek Dhanotia

Citations in the corpus

• TPP: Transparent Page Placement for CXL-Enabled Tiered-Memory (2022, background): “With the advent of CXL technologies, hyperscalers are embracing CXL-enabled heterogeneous tiered-memory system where different memory tier has different performance characteristics [41, 52].”