The effect of LUT and cluster size on deep-submicron FPGA performance and density

By E. Ahmed, J. Stephanie Rose. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2000

525 citations recorded by the source corpus.

In this paper, we revisit the field-programmable gate-array (FPGA) architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cluster-based island-style FPGAs (Betz et al. 1997) we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic density of an FPGA. We use a fully timing-driven experimental flow (Betz et al. 1997), (Marquardt, 1999) in which a set of benchmark circuits are synthesized into different cluster-based (Betz and Rose, 1997, 1998) and (Marquardt, 1999) logic block architectures, which contain groups of LUTs and flip-flops. Across all architectures with LUT sizes in the range of 2 to 7 inputs, and cluster size from 1 to 10 LUTs, we have experimentally determined the relationship between the number of inputs required for a cluster as a function of the LUT size (K) and cluster size (N). Second, contrary to previous results, we have shown that clustering small LUTs (sizes 2 and 3) produces better area results than what was presented in the past. However, our results also show that the performance of FPGAs with these small LUT sizes is significantly worse (by almost a factor of 2) than larger LUTs. Hence, as measured by area-delay product, or by performance, these would be a bad choice. Also, we have discovered that LUT sizes of 5 and 6 produce much better area results than were previously believed. Finally, our results show that a LUT size of 4 to 6 and cluster size of between 3-10 provides the best area-delay product for an FPGA.

View Paper: https://www.semanticscholar.org/paper/5ffa17bc601687087d9d7206b06df55dd9ffdf0c

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Citations in the corpus

The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory (2010, background): “... asthe squareofthenumberofrowsorcolumns,whiletheperiphery grows only linearly with the number of rows/columns, the larger the memory array the less important the overhead for theperipherybecomes.ThiscanbeaproblemthoughforLUT operations because if the LUTs become too large there is a higher likeli”
FPGA Architecture: Survey and Challenges (2008, unknown): “The cost of this flexibility is incurred by the FPGA vendor, who must support a larger number of devices.”
CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices (2005, background): “Increasing the memory array size up to the optimum value calculated in [16] is not a viable option either, because the LUT performance scales (approximately) only as a log of its capacity [17].”