CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices

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On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex (2011, unknown): “The output node connects to a thin line tilted slightly with respect to the CMOS tile (as in CMOL; Strukov and Likharev, 2005), so that it does not intersect with any other neuron output node in the CMOS tile.”
Towards evolving spiking networks with memristive synapses (2011, background): “We are particularly interested in the latter field, where the memristor can function as a synapse between - for example - Complementary Metal-Oxide Semiconductor (CMOS) neurons [ 4 ].”
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies (2014, methodology): “In [3], memristors are used as a reconfigurable switch.”
Nanowire Transistor Performance Limits and Applications (2008, unknown): “[115], [118].”
Nanoelectronics from the bottom up. (2007, background): “For more general logic operations, hybrid CMOS/crossbar structures may be require”
Nano/CMOS architectures using a field-programmable nanowire interconnect (2007, methodology): “The junction configuration uses the same scheme proposed for use in CMOL [20].”