A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
By C. Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, W. Hafez, M. Jang, M. Kang, K. Komeyli and 13 more. International Electron Devices Meeting, 2012
295 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/5c42cb2669691a21a2651638e9c3feb104a506a7
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In Electrical and Electronic Engineering
Citations in the corpus
- Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors (2013, methodology): “In this way, the ease of fabrication on standard Si substrates and the scaling advantages of the FinFET architecture can be combined, resulting in the first adoption of bulk FinFETs by a commercial manufacturer at the 22 nm CMOS technology node [14].”