DAVE: Deriving Automatically Verilog from English

By Hammond A. Pearce, Benjamin Tan, Ramesh Karri. 2020

100 citations recorded by the source corpus.

Specifications for digital systems are provided in natural language, and engineers undertake significant efforts to translate these into the programming languages understood by compilers for digital systems. Automating this process allows designers to work with the language in which they are most comfortable - the original natural language - and focus instead on other downstream design challenges. We explore the use of state-of-the-art machine learning (ML) to automatically derive Verilog snippets from English via fine-tuning GPT-2, a natural language ML system. We describe our approach for producing a suitable dataset of novice-level digital design tasks and provide a detailed exploration of GPT-2, finding encouraging translation performance across our task sets (94.8 % correct), with the ability to handle both simple and abstract design tasks.

Subfields: Information Systems, Materials Chemistry

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Information Systems

1. Siddharth Garg
2. Ramesh Karri
3. Hammond A. Pearce
4. Brendan Dolan-Gavitt
5. Benjamin Tan
6. Robert Kirby
7. Baleegh Ahmad
8. Bryan Catanzaro

In Materials Chemistry

1. Siddharth Garg
2. Ramesh Karri
3. Hammond A. Pearce

Citations in the corpus

• Asleep at the Keyboard? Assessing the Security of GitHub Copilot’s Code Contributions (2021, neutral): “These models can perform language tasks such as translation and answering questions from the CoQA [19] dataset; after fine-tuning on specialized datasets, the models can undertake tasks such as code completion [2] and hardware design [20].”
• ChipNeMo: Domain-Adapted LLMs for Chip Design (2023, background): “Early works such as Dave [52] first explored the possibility of generating Verilog from English with a language model (GPT-2).”
• VeriGen: A Large Language Model for Verilog Code Generation (2023, methodology): “Second, while fine-tuning a given LLM over a Verilog corpus can aid in its authorship of HDL [24], this requires a large dataset of Verilog.”
• Chip-Chat: Challenges and Opportunities in Conversational Hardware Design (2023, methodology): “The first work exploring LLMs for use in the hardware domain was by Pearce et al. [15].”