Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory
By Hiroyasu Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Yoshiaki Fukuzumi, M. Sato, Y. Nagata, Yasuyuki Matsuoka and 3 more. 2007 IEEE Symposium on VLSI Technology, 2007
402 citations recorded by the source corpus.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/599502235b51a0d08a2bb5a1549d3cb8f230af1b
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In Biomedical Engineering
In Electrical and Electronic Engineering
- Shimeng Yu
- Pai-Yu Chen
- J. Joshua Yang
- Qiangfei Xia
- Zhongrui Wang
- Hao Jiang
- A. Padilla
- Michele M. Franceschini
Citations in the corpus
- Emerging Memory Technologies: Recent Trends and Prospects (2016, background): “State-of-the-art two-dimensional (2D) NAND flash has been scaled down to around 15 nm in 2015, while the 3D stackable NAND flash is emerging [54], [55].”
- Three-dimensional memristor circuits as complex neural networks (2020, background): “The 3D design provides a high degree of functional complexity, which goes beyond the purpose of increasing packing density in conventional 3D architectures 20–26 and opens a critical avenue to using memristors for neuromorphic computing.”
- Phase change memory technology (2010, background): “Worse yet, such few-electron problems will only increase with further dimensional scaling, leading Flash researchers to explore even more complicated schemes for FinFET Flash devices[21, 22] or 3-D stacking of Flash memory[23–26].”