Dual work function metal gate CMOS technology using metal interdiffusion

By I. Polishchuk, P. Ranade, Tsu-Jae King, Chenming Hu. IEEE Electron Device Letters, 2001

180 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/58cf47ecbd3e0ee2020356d75eeacba27255f744

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In Electrical and Electronic Engineering

1. Mansun Chan
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Citations in the corpus

• A Junctionless Nanowire Transistor With a Dual-Material Gate (2012, methodology): “and metal interdiffusion techniques [16] and a metal wet etch process [17] have been used to fabricate the dual-metal-gate work-function CMOS down to the gate length of 45 nm.”
• An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design (2012, methodology): “For the feasibility of the GME architecture, several integration schemes have been suggested, such as tilt angle evaporation metal gate deposition [16], metal interdiffusion process [17],”