Serving DNNs in Real Time at Datacenter Scale with Project Brainwave

By Eric S. Chung, J. Fowers, Kalin Ovtcharov, Michael Papamichael, Adrian M. Caulfield, Todd Massengill, Ming Liu, Daniel Lo, Shlomi Alkalay, M. Haselman and 33 more. IEEE Micro, 2018

325 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Information Systems

View Paper: https://www.semanticscholar.org/paper/57f1e3397004ea0ce2877e07f0cbbfbb3045de41

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Citations in the corpus

Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, methodology): “5 Flexible Accelerator In this experiment, we consider accelerators where the PE array dimensions are configurable, such as FPGAs [17], CGRA [57], or programmable accelerators [4, 120, 125].”
TT-Rec: Tensor Train Compression for Deep Learning Recommendation Models (2021, background): “In response, there is considerable interest to design domainspecific accelerators and at-scale infrastructures (Alibaba, 2019; Amazon, 2019; Chung et al., 2018; Fowers et al., 2018; Hazelwood et al., 2018; Jouppi et al., 2017; Lee & Rao, 2019; Mattson et al., 2019; NVIDIA, 2020a; Ovtcharov et al.,…”
The Architectural Implications of Facebook's DNN-Based Personalized Recommendation (2019, background): “As web-based applications continue to expand globally, so does the amount of compute and storage resources devoted to deep learning training and inference [17, 30, 36].”
A Configurable Cloud-Scale DNN Processor for Real-Time AI (2018, methodology): “We have developed a full-system architecture for DNN inference that uses a different approach [1], [2].”
Sponge Examples: Energy-Latency Attacks on Neural Networks (2020, background): “Hardware dedicated to deep learning is now pervasive in data centers, with examples including Big Basin at Facebook [15], BrainWave at Microsoft [16], and racks of TPUs at Google [11, 17]; the underlying hardware on these systems are either commodity hardware (Big Basin), reconfigurable hardware (FP”
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference (2019, unknown): “erations in general-purpose workloads whereas PUMA optimizes crossbars for MVM operations prevalent in machine learning and uses digital VFUs for vector operations rather than crossbars. Chung et al. [24] propose Brainwave, which is a spatial accelerator built with FPGAs. Compared to Brainwave, a PU”
Seer: Leveraging Big Data to Navigate the Complexity of Performance Debugging in Cloud Microservices (2019, methodology): “inference, either using a special-purpose design like the Tensor Processing Unit (TPU) from Google [55], or using reconfigurable FPGAs, like Project Brainwave from Microsoft [25].”
Hardware/Software Co-Exploration of Neural Architectures (2019, unknown): “performance, and energy efficiency, in particular for low-batch inferences [19], [20].”
Building Efficient Deep Neural Networks With Unitary Group Convolutions (2018, methodology): “On the other hand, we believe the Hadamard transform might be useful for specialized DNN accelerators implemented with FPGAs [3] or ASICs [11].”
An Open-Source Benchmark Suite for Microservices and Their Hardware-Software Implications for Cloud & Edge Systems (2019, background): “This includes analyzing the cycle breakdown in modern servers, examining whether big or small cores are preferable [25, 35, 41, 42, 46– 48], determining the pressure microservices put on instruction caches [37, 52], and exploring the potential they have for hardware acceleration [24, 27, 38, 49, 71]”
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search (2019, methodology): “To illustrate our framework, we choose to use Field programmable gate array (FPGA) as a vehicle, as it has gradually become one of themost popular platforms to implement DNNs due to its high performance and energy efficiency, in particular for low-batch real-time applications [2].”