Current Status of Research and Development for Three-Dimensional Chip Stack Technology

By Kenji Takahashi Kenji Takahashi, Hiroshi Terao Hiroshi Terao, Yoshihiro Tomita Yoshihiro Tomita, Yasuhiro Yamaji Yasuhiro Yamaji, Masataka Hoshino Masataka Hoshino, Tomotoshi Sato Tomotoshi Sato, Tadahiro Morifuji Tadahiro Morifuji, Masahiro Sunohara Masahiro Sunohara, Manabu Bonkohara Manabu Bonkohara. 2001

156 citations recorded by the source corpus.

Subfields: Automotive Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/4675dd4e3baa42cc7eee825ec8823ae21d1e7bb4

How researchers see this paper

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1. Joungho Kim
2. Jin Yu
3. Taesung Oh
4. Chunghyun Ryu
5. D. Jang
6. Kwangyong Lee
7. B. Cho
8. W. Lee

Citations in the corpus

• Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV) (2007, methodology): “As a new interconnection technology for 3D stacked packages, chip-to-chip vertical interconnection technology using TSV has been proposed [8-10].”