Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN

By P. Bosshart, Glen Gibb, Hun-Seok Kim, George Varghese, Nick McKeown, M. Izzard, Fernando A. Mujica, Mark A. Horowitz. Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, 2013

1,172 citations recorded by the source corpus.

In Software Defined Networking (SDN) the control plane is physically separate from the forwarding plane. Control software programs the forwarding plane (e.g., switches and routers) using an open interface, such as OpenFlow. This paper aims to overcomes two limitations in current switching chips and the OpenFlow protocol: i) current hardware switches are quite rigid, allowing ``Match-Action'' processing on only a fixed set of fields, and ii) the OpenFlow specification only defines a limited repertoire of packet processing actions. We propose the RMT (reconfigurable match tables) model, a new RISC-inspired pipelined architecture for switching chips, and we identify the essential minimal set of action primitives to specify how headers are processed in hardware. RMT allows the forwarding plane to be changed in the field without modifying hardware. As in OpenFlow, the programmer can specify multiple match tables of arbitrary width and depth, subject only to an overall resource limit, with each table configurable for matching on arbitrary fields. However, RMT allows the programmer to modify all header fields much more comprehensively than in OpenFlow. Our paper describes the design of a 64 port by 10 Gb/s switch chip implementing the RMT model. Our concrete design demonstrates, contrary to concerns within the community, that flexible OpenFlow hardware switch implementations are feasible at almost no additional cost or power.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/3d4d2916c63f4bc19b8f18819b2d6b1bfe895b6d

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Citations in the corpus

SilkRoad: Making Stateful Layer-4 Load Balancing Fast and Cheap Using Switching ASICs (2017, methodology): “Throughout the simulations, we consider the SRAM word of 112 bits as used in [19].”
One Sketch to Rule Them All: Rethinking Network Flow Monitoring with UnivMon (2016, methodology): “Finally, for [R3], we note that even emerging ﬂexible switches [3,12,13] have constraints on the types of operations that they can support.”
The Road to SDN (2013, background): “11 Also, the concepts of isolation of experimental traffic from normal traffic—which have their roots in active networking— also appear front and center in design documents for OpenFlow 51 and other SDN technologies (e.g., FlowVisor 29 ).”
Programmable Packet Scheduling at Line Rate (2016, methodology): “For example, RMT’s match-action pipeline uses 4000 1-bit wires between a a pair of pipeline stages to move its 4K packet header vector between stages [17].”
In-band Network Telemetry via Programmable Dataplanes (2015, background): “At the highend, new programmable protocol-independent switch chips promise multi-Tb/s of packet processing [6, 4, 2].”
Packet-Level Telemetry in Large Datacenter Networks (2015, methodology): “In the future, we plan to extend Everﬂow to make use of the features offered by new programmableswitching ASIC [4, 20], including hardware timestamping and packet metadata matching.”
A roadmap for traffic engineering in SDN-OpenFlow networks (2014, methodology): “Although some methods, such as the RMT (Reconfigurable Match Tables) model [69] and the FlowAdapter [70], have been proposed to address some challenging issues caused by the resource constraint of TCAM-based tables, there are some open issues with the implementation of a multiflow table pipeline in ”
IncBricks: Toward In-Network Computation with an In-Network Cache (2017, background): “Programmable switches add reconﬁgurability in their forwarding plane in order to overcome limitations of previous ﬁxed-function switches [16].”
OpenState: programming platform-independent stateful openflow applications inside the switch (2014, background): “Microsoft Research, UK a c m s i g c o m m”
HULA: Scalable Load Balancing Using Programmable Data Planes (2016, methodology): “To illustrate this, we prototype HULA in the recently proposed P4 language [19] that explicitly targets such programmable data planes.”
5G roadmap: 10 key enabling technologies (2016, background): “Also, new architectures that speedup switches and base stations need to be developed [39] .”
Heavy-Hitter Detection Entirely in the Data Plane (2016, methodology): “The overhead on the switch includes the total amount of memory for the data structure, the number of matching stages used in the switch pipeline (constrained by a switch-specific maximum, say 16 [7]).”
Sonata: query-driven streaming network telemetry (2018, background): “5–32 Mb memory for each stage [9] Ordered set of dataflow operators for query q .”
Language-Directed Hardware Design for Network Performance Monitoring (2017, methodology): “Programmable switches [3, 13, 25] now support flexible parsing [39], header processing [33, 56], and scheduling [57].”
E2: a framework for NFV applications (2015, background): “Akin to several recent network management systems [12, 15–17, 20, 37, 49], E2 provides a declarative interface through which the global SDN controller tells each E2 cluster how trafﬁc should be processed.”