Corey: An Operating System for Many Cores
By Silas Boyd-Wickizer, Haibo Chen, Rong-Xin Chen, Yandong Mao, M. Frans Kaashoek, Robert Morris, A. Pesterev, Lex Stein, Ming Wu, Yue-hua Dai and 2 more. USENIX Symposium on Operating Systems Design and Implementation, 2008
408 citations recorded by the source corpus.
View Paper: https://www.semanticscholar.org/paper/3864e4bef3ef5fb9feb6718d22bd918638743121
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
- Silas Boyd-Wickizer
- Daniel Sánchez
- Christos Kozyrakis
- M. Frans Kaashoek
- Robert Morris
- Mohammad Dashti
- Austin T. Clements
- Andrew Baumann
Citations in the corpus
- An Analysis of Linux Scalability to Many Cores (2010, methodology): “, Barrelfish [11], Corey [15], and fos [53]).”
- Sora (2009, background): “Second, previous work on multi-core OSes also suggests that isolating applications into different cores may have better performance compared to symmetric scheduling, since an effective use of cache resources and a reduction in locks can outweigh dedicating cores [10].”
- ZSim: fast and accurate microarchitectural simulation of thousand-core systems (2013, methodology): “Events are generated frequently and dynamically, so we use per-core slab allocators and recycle slabs in LIFO order as soon as their interval is fully simulated to avoid the performance overheads and scalability issues of generic dynamic memory allocation.”
- The multikernel: a new OS architecture for scalable multicore systems (2009, background): “The tradeo ff between these two is similar to that investigated in Corey [13]; the former is typically more e ffi cient, however the latter may reduce cross-processor TLB invalidations (because it is possible to track which processors may have cached a mapping), and is also the only way to share an add”
- Traffic management: a holistic approach to memory placement on NUMA systems (2013, background): “On NUMA systems that are built today, remote wire delays add at most 30% to the cost of a memory access [7].”