DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings

By Aayush Gupta, Youngjae Kim, Bhuvan Urgaonkar. International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

905 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/334535d6a9c96cb60c949d5409db1e3420908c0f

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Onur Mutlu
2. Yixin Luo
3. Saugata Ghose
4. Yu Cai
5. Erich F. Haratsch
6. Xiaodong Zhang
7. Feng Chen
8. Sudipta Sengupta

In Hardware and Architecture

1. Onur Mutlu
2. Saugata Ghose
3. Yixin Luo
4. Yu Cai
5. Erich F. Haratsch
6. Xiaodong Zhang
7. Feng Chen
8. Wen-mei W. Hwu

Citations in the corpus

• ChunkStash: Speeding Up Inline Storage Deduplication Using Flash Memory (2010, background): “However, for the workloads with random access patterns, these schemes show very poor performance [21, 23, 26, 28, 32].”
• DeepStore: In-Storage Acceleration for Intelligent Queries (2019, methodology): “The SSD controller contains 2-4 embedded CPU cores that execute the SSD management with Flash Translation Layer (FTL), whose functionalities include parsing block I/O commands, garbage collection, and wear-leveling [47].”
• CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives (2011, methodology): “We can also apply an approach similar to DFTL [23] to further reduce the memory demand by selectively maintaining the most frequently accessed entries of the mapping tables in memory.”
• Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives (2017, background): “…of the FTL is to manage the mapping of logical addresses (i.e., the address space utilized by the host) to physical addresses in the underlying flash memory (i.e., the address space for actual locations where the data is stored, visible only to the SSD controller) for each page of data [40, 58].”
• SCORE (2018, methodology): “In this article, we assume a page-level mapping, because it has been widely used due to better addressing flexibility and performance [23].”