A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

By C. Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, V. Bhagwat, J. Birdsall, N. Bisnik, M. Bühler, V. Chikarmane, G. Ding and 46 more. International Electron Devices Meeting, 2017

364 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/3028e8754642eae0c534ca3c7d7f54f0ededb36a

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In Electrical and Electronic Engineering

1. Menno Veldhorst
2. Lieven M. K. Vandersypen
3. Edward J. Nowak
4. Roza Kotlyar

Citations in the corpus

• Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures (2019, methodology): “Hardware DIBL data supports these predictions [5]–[24].”
• Qubits made by advanced semiconductor manufacturing (2021, background): “Today, industry is able to make uniform transistors with gate lengths of several tens of nanometers and spaced apart by 34 nm (fins) to 54 nm (gates), feature sizes that are well below the 193 nm wavelength of the light used in the lithography process [35].”