Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

By C. Selvanayagam, J. H. Lau, Xiaowu Zhang, S.K.W. Seah, K. Vaidyanathan, T. Chai. IEEE Transactions on Advanced Packaging, 2009

230 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials

View Paper: https://www.semanticscholar.org/paper/256f46104a01b54deb03f050195b7f86ec06b39d

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In Electrical and Electronic Engineering

1. Rui Huang

Citations in the corpus

• Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects (2011, background): “…the coefficients of thermal expansion (CTEs) of the via materials and Si, thermal stresses are ubiquitously induced during processing and thermal cycling of TSV structures, which can potentially degrade the performance of stress-sensitive devices around the TSVs [8], [9] or drive crack growth in 3-”
• Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV) (2009, background): “Tremendous research effort [1-7] has been devoted to the development and improvement of various TSV fabrication process steps.”