Why systolic architectures?

By H. T. Kung. 1982

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Citations in the corpus

In-datacenter performance analysis of a tensor processing unit (2017, neutral): “[2] Slides referenced from prof Zhiru Zhang”
Deep Learning with Limited Numerical Precision (2015, background): “The DSP units within the FPGA are organized as a massively parallel 2-dimensional systolic array (SA) (Kung, 1982) of size n such that n 2 840.”
End-to-End Learning of Energy-Constrained Deep Neural Networks (2018, background): “Systolic arrays [22] have long been know as effective yet simple designs for matrix multiplication.”
Efficient Deep Learning: A Survey on Making Deep Learning Models Smaller, Faster, and Better (2021, background): “The core architecture of the TPU chips leverages the systolic array design [79, 80], where a large computation is split across a mesh-like topology, where each cell computes a partial result and passes it on to the next cell in the order, every clock step (in a rhythmic manner analogous to the systo”
Energy-Constrained Compression for Deep Neural Networks via Weighted Sparse Projection and Layer Input Masking (2018, methodology): “Without losing generality, we model the DNN energy consumption after the popular systolic array hardware architecture (Kung, 1982) that is increasingly adopted in today’s DNN hardware chips such as Google’s Tensor Processing Unit (TPU) (Jouppi et al., 2017), NVidia’s Tensor Cores, and ARM’s ML…”
Benchmarking TPU, GPU, and CPU Platforms for Deep Learning (2019, background): “TPU is well suited for large batch training, because systolic arrays are very good at increasing throughput [35].”
On-chip training of recurrent neural networks with limited numerical precision (2017, methodology): “We also implement our hardware on systolic array [21]– [22] to analyze entire system performance.”
Unifying computers and dynamical systems using the theory of synchronous concurrent algorithms (2009, background): “Further examples and discussion can be found in [37,44,72,45,50,16,51,46,43].”
NeuFlow: A runtime reconfigurable dataflow processor for vision (2011, background): “Several types of grids have been proposed in the past [8, 14, 17], often trying to solve the dual latency/throughput problem, and often providing a computing fabric that is too rigid.”
Knowledge Graphs (2020, unknown): “These graph parallel frameworks apply a systolic abstraction [303] based on a directed graph, where nodes are processors that can send messages to other nodes along edges.”
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic (2008, background): “In addition, they also possess significant potential to yield high-throughput rate by exploiting high-level of concurrency using pipelining or parallel processing or both [3].”
Collision-Based Computing (2002, methodology): “Since many of the necessary technicalities have been thoroughly covered in a companion paper, "Reversible Computing" [26], here we shall have more freedom to present the ideas of conservative logic in a discursive fashion, stressing physical motivation and often making appeal to intuition.”
Randomness In Neural Network Training: Characterizing The Impact of Tooling (2021, background): “, 2017) is a custom ASIC leverage systolic arrays (Kung, 1982) in matrix unit (MXU) to provide massive computation throughput with a singlethreaded, deterministic computation model.”
Kernel Methods and Machine Learning (2014, background): “Show that systolic arrays are amenable to tensor-based algorithms for classification [133, 134].”