Asynchronous Techniques for System-on-Chip Design

By Alain J. Martin, M. Nyström. Proceedings of the IEEE, 2006

319 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/0c3e21a8122772738f23e024394749642a6b252f

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Kwabena A. Boahen
2. Giacomo Indiveri
3. Fabio Stefanini
4. Saber Moradi
5. Ning Qiao

In Electrical and Electronic Engineering

1. Giacomo Indiveri
2. Tobi Delbruck
3. B. Linares‐Barranco
4. T. Serrano‐Gotarredona
5. Christoph Posch
6. Shih-Chii Liu
7. Fabio Stefanini
8. Ning Qiao

In Hardware and Architecture

1. Giacomo Indiveri
2. Fabio Stefanini
3. Saber Moradi
4. Ning Qiao

Citations in the corpus

• On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex (2011, background): “A better understanding of asynchronous design (Sparsø and Furber, 2001; Martin and Nyström, 2006) leading to robust unarbitrated (Mortara et al., 1995) and arbitrated (Boahen, 1996, 2000) asynchronous event readout, combined with the availability of user-friendly FPGA external support for…”
• Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations (2014, methodology): “All this digital circuitry is event drivenVonly active when a spike occursVwith its logic synthesized following Martin’s procedure for asynchronous circuits [60], [61].”
• Retinomorphic Event-Based Vision Sensors: Bioinspired Cameras With Spiking Output (2014, background): “A better understanding of asynchronous design [34], [35] leading to robust unarbitrated [36] and arbitrated [17] asynchronous event readout, combined with the availability of userfriendly field-programmable gate array (FPGA) external support for interfacing and new submicrometer technologies allowin”
• A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) (2017, methodology): “The asynchronous circuits that implement the R1, R2, and R3 routers, and the overall routing architecture, were synthesized using the QDI approach [23], by following the Communicating Hardware Processes (CHP) [24] and Handshaking Expansion (HSE) formalism [25] (see also Appendix C for the most commo”