A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

By Saber Moradi, Ning Qiao, Fabio Stefanini, Giacomo Indiveri. IEEE Transactions on Biomedical Circuits and Systems, 2017

573 citations recorded by the source corpus.

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

Subfields: Cognitive Neuroscience, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/d7a0de77a7a25943cb99d8301a839cfe54bc6e7b

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In Cognitive Neuroscience

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Citations in the corpus

Deep Learning With Spiking Neurons: Opportunities and Challenges (2018, background): “…no results for deep SNNs are shown yet (Park et al., 2014; Lin et al., 2018), or the presented neuron and synapse count is too small to show competitive results (Pfeil et al., 2013a; Schmuker et al., 2014; Indiveri et al., 2015; Qiao et al., 2015; Moradi et al., 2017; Petrovici et al., 2017).”
A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS (2018, methodology): “SOP energy of 30 pJ can be estimated from [24] using the measured 800-μW power consumption with all 1k neurons spiking at 100 Hz with 25% connectivity (26.”
Opportunities for neuromorphic computing algorithms and applications (2022, background): “Both industry and academia have taken an interest in neuromorphic systems: in industry, some examples include IBM’s TrueNorth 23 and Intel’s Loihi 7 , and there are also a variety of academic efforts, including DYNAPs 24 , Neurogrid 25 , IFAT 13 and BrainScales-2 26 .”
Event-Based Vision: A Survey (2019, background): “Processor SpiNNaker TrueNorth Loihi DYNAP Braindrop Reference [257] [258] [259] [260] [261]”