Symmetrical PLL for SISO Impedance Modeling and Enhanced Stability in Weak Grids

By Dongsheng Yang, Xiongfei Wang, Fangcheng Liu, Kai Xin, Yunfeng Liu, Frede Blaabjerg. IEEE transactions on power electronics, 2020

145 citations recorded by the source corpus.

This paper proposes a symmetrical phase-locked loop (PLL) that can eliminate the frequency-coupling terms caused by the asymmetric dynamics of conventional PLLs. In the approach, a concept of complex phase angle vector with both real and imaginary phase components is introduced, which enables to control the direct- and quadrature-axis components with symmetrical dynamics. The small-signal impedance model that characterizes the dynamic effect of the symmetrical PLL on the current control loop is also derived, which, differing from the conventional multiple-input multiple-output impedance matrix, is in a single-input single-output (SISO) form based on complex transfer functions. This SISO representation allows for a design-oriented analysis. Moreover, the undesired sub-synchronous oscillation caused by the conventional asymmetrical PLL can be avoided, and the classical SISO impedance shaping can be utilized to cancel the negative resistor behavior caused by PLL; thus can greatly enhance the grid synchronization stability under weak grid conditions. The effectiveness of the theoretical analysis is validated by experimental tests.

Subfields: Control and Systems Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/f97b608f14f482d8da7937cd777d216f37e5c9a8

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In Control and Systems Engineering

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Citations in the corpus

Grid-Synchronization Stability of Converter-Based Resources—An Overview (2020, background): “(c) Symmetrical PLL for SISO-based impedance shaping [39].”