A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
By Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang and 7 more. IEEE International Solid-State Circuits Conference, 2018
300 citations recorded by the source corpus.
Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/e6fbb8d3bededb92d1e311fbb6b2625453fc6642
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In Computer Vision and Pattern Recognition
In Electrical and Electronic Engineering
Citations in the corpus
- Hardware/Software Co-Exploration of Neural Architectures (2019, unknown): “Second, innovations on computing architecture achieves great success for executing inference phase of neural networks [44], we plan to apply the proposed framework to co-explore neural architectures with the novel computing architectures (e.g., computing-in-memory).”
- Three-dimensional memristor circuits as complex neural networks (2020, methodology): “It has been implemented in standard 2D memristor crossbar arrays, but each array can only process convolutions from the same input pixels due to the aforementioned full connectivity 31,32 .”
- In-Memory Computing: Advances and prospects (2019, background): “Thus, IMC can apply to any memory technology integrated in such a structure [8]–[10].”
- Neuro-inspired computing chips (2020, methodology): “Although applying heuristic compensation by adding scaling factors to the output terminal can mitigate this effect for some specific neural networks 66 , The past milestones 11,12,17,21,23,63,71,105 and future prospects are illustrated.”