Secure scan: a design-for-test architecture for crypto chips

By Bo Yang, Kaijie Wu, Ramesh Karri. Proceedings - Design Automation Conference, 2005

319 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/e34866355fbabc9cc71b1432c819dfbe8542502f

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Artificial Intelligence

1. Ramesh Karri
2. Masoud Rostami
3. Farinaz Koushanfar

In Hardware and Architecture

1. Ramesh Karri
2. Masoud Rostami
3. Farinaz Koushanfar
4. Jeyavijayan Rajendran
5. Ozgur Sinanoglu
6. Arturo Geigel

Citations in the corpus

• A Primer on Hardware Security: Models, Methods, and Metrics (2014, background): “5) Secure Scan Chains: In a secure scan approach, mirror key registers are used in sensitive parts of the circuits [102].”