Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC
By Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr. International Conference on Field-Programmable Technology, 2016
318 citations recorded by the source corpus.
Subfields: Artificial Intelligence, Computer Vision and Pattern Recognition, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/db4e71799cabeebf5530c26cccda0f8023c5af9f
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Artificial Intelligence
- Sparsh Mittal
- Debbie Marr
- Ganesh Venkatesh
- Kees A. Vissers
- Eriko Nurvitadhi
- Philip Heng Wai Leong
- Giulio Gambardella
- Michaela Blott
In Computer Vision and Pattern Recognition
- Sparsh Mittal
- Debbie Marr
- Kenneth O'Brien
- Ganesh Venkatesh
- Kees A. Vissers
- Eriko Nurvitadhi
- Philip Heng Wai Leong
- Giulio Gambardella
In Hardware and Architecture
Citations in the corpus
- FINN-R (2018, result): “We constrain our comparison to only measured results and exclude extrapolated numbers ([39, 41, 44, 45]).”
- A survey of FPGA-based accelerators for convolutional neural networks (2018, methodology): “Some techniques decide about using spatial or Winograd CONV for each layer [34] since the Winograd - 1 is represented using 0. c Implementing binarized MM using an LUT (OUT is in 2’s complement form) [26] algorithm reduces computations but increases the BW pressure.”
- FINN: A Framework for Fast, Scalable Binarized Neural Network Inference (2016, background): “[19] compares binary matrix-vector operation performance and efficiency on FPGA, ASIC, GPU and CPU.”
- Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? (2017, methodology): “The work in [28][30] compare Neural Networks implemented on CPU, FPGA, GPU, and ASIC.”