A reduced complexity decoder architecture via layered decoding of LDPC codes
By D. Hocevar. IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004., 2004
604 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/d779732f054d11c338f33e377705728f04bf800c
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Shrinivas Kudekar
- T. Richardson
- Marc P. C. Fossorier
- Rüdiger L. Urbanke
- Amin Shokrollahi
- David John Cameron MacKay
- Andrea J. Goldsmith
- Gianluigi Liva
In Electrical and Electronic Engineering
- Shrinivas Kudekar
- T. Richardson
- Marc P. C. Fossorier
- Rüdiger L. Urbanke
- Amin Shokrollahi
- David John Cameron MacKay
- Andrea J. Goldsmith
- Gianluigi Liva
Citations in the corpus
- Design of Low-Density Parity Check Codes for 5G New Radio (2018, background): “Quasi and Full Row Orthogonality: In a typical hardware implementation of a quasi-cyclic LDPC decoder [9], there are Z processors, where Z corresponds to the maximum lift value.”