HBM (High Bandwidth Memory) DRAM Technology and Architecture

By Hongshin Jun, Jin-Hee Cho, Kangseol Lee, H.-Y Son, Kwiwook Kim, H. Jin, Keith Kim. International Memory Workshop, 2017

247 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials

View Paper: https://www.semanticscholar.org/paper/d3496fc84745e5b647b51040fc391c89b1b42b94

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Sheng-Chun Kao
2. Tushar Krishna

Citations in the corpus

• Domain-specific Genetic Algorithm for Multi-tenant DNNAccelerator Scheduling (2021, background): “0 [78] BW; at the Large accelerator, we consider the BW to be range from 1GB/s to 256GB/s, which is the range of DDR4-DDR5 [70] and HBM BW [48] and PCIe3.”