Packet Transactions: High-Level Programming for Line-Rate Switches
By Anirudh Sivaraman, Alvin Cheung, Mihai Budiu, Changhoon Kim, Mohammad Alizadeh, Hari Balakrishnan, George Varghese, Nick McKeown, Steve Licking. Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, 2015
344 citations recorded by the source corpus.
Many algorithms for congestion control, scheduling, network measurement, active queue management, and traffic engineering require custom processing of packets in the data plane of a network switch. To run at line rate, these data-plane algorithms must be implemented in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chips. The key challenge is that many data-plane algorithms create and modify algorithmic state. To achieve line-rate programmability for stateful algorithms, we introduce the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated chip-area overhead.
Subfields: Computer Networks and Communications
View Paper: https://www.semanticscholar.org/paper/c6539370fbe770ff9ad9650beeca5f817e6390c7
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Jennifer Rexford
- Anirudh Sivaraman
- Changhoon Kim
- Mohammad Alizadeh
- Hari Balakrishnan
- Venkat Arun
- Nick McKeown
- Srinivas Narayana
Citations in the corpus
- Programmable Packet Scheduling at Line Rate (2016, methodology): “Domino proposes atoms that are expressive enough to support many data-plane algorithms and small enough to implement at 1 GHz .”
- Heavy-Hitter Detection Entirely in the Data Plane (2016, background): “Such conditional state updates are feasible at line rate [19, 40].”
- Scaling Distributed Machine Learning with In-Network Aggregation (2019, neutral): “Thus, the model-update vector and all other packet headers must fit within this limited budget, which is today on the order of a few hundred bytes; ASIC design constraints make it unlikely that this will increase dramatically in the future [10, 16, 85].”
- Language-Directed Hardware Design for Network Performance Monitoring (2017, methodology): “Programmable switches [3, 13, 25] now support flexible parsing [39], header processing [33, 56], and scheduling [57].”