A VLSI architecture for high-performance, low-cost, on-chip learning

By D. Hammerstrom. 1990

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Citations in the corpus

Deep Learning with Limited Numerical Precision (2015, methodology): “Hammerstrom (Hammerstrom, 1990) presents a framework for on-chip learning using 8 to 16 bit fixed-point arithmetic.”
Up or Down? Adaptive Rounding for Post-Training Quantization (2020, neutral): “Hammerstrom (1990)”
Hardware-oriented Approximation of Convolutional Neural Networks (2016, background): “Moreover, it has been shown that ﬁxed point arithmetic is adequate for neural network computation (Hammerstrom, 1990).”
Zip nets: Efficient associative computation with binary synapses (2010, background): “A neural asso- ciative memory stores the memories in the synaptic weights A connecting neuron layer u to neuron layer v.”
Artificial neural networks in hardware: A survey of two decades of progress (2010, unknown): “Possible solutions include use of look-up tables [85] [86] and piecewise linear approximating functions [87].”
Programmable Neurocomputing (methodology): “Example SIMD neurocomputers include the CNAPS systems [6] from Adaptive Solutions and the SNAP [10] system from HNC.”
Recent Advances in Convolutional Neural Network Acceleration (2018, methodology): “ncreases the computation workload and memory size for the neural networks. However, arithmetic operations in ﬁxed-point instead of ﬂoatingpoint can achieve enough good performance for neural networks [77]. A 16-bit ﬁxed-point representation method is proposed by using stochastic rounding for trainin”
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey (2020, background): “Due to the limited space, we just review the recent accelerators that can support large-scale neural networks and ignore the early ones [259], [260].”
Memory Capacities for Synaptic and Structural Plasticity (2010, background): “One big advantage of the Willshaw model is that there are obvious realizations for such architectures (Palm & Palm, 1991; Hammerstrom, 1990; Hammerstrom, Gao, Zhu, & Butts, 2006).”
Efficient Associative Computation with Discrete Synapses (2016, methodology): “Associative neurocomputers are one such alternative paradigm in which, unlike the classical von Neumann machine, computation and data storage are not separated (Steinbuch, 1961; Willshaw, Buneman, & LonguetHiggins, 1969; Palm, 1982; Palm & Palm, 1991; Hammerstrom, 1990; Heittmann & Rückert, 2002; Ch”
Synchronization and pattern separation in spiking associative memories and visual cortical areas (2004, background): “[62]) where the individual processors have relatively limited working memory.”
A Survey of Neuromorphic Computing and Neural Networks in Hardware (2017, unknown): “systems [502], [591], [628], [754], [755], [812], [868], [976],”
Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations (2014, methodology): “In SS, first realized 24 years ago [22], [23], only N electronic circuits are required to fully connect N neurons, rather than N(2), a feature shared with SD [Fig.”