Surface participation and dielectric loss in superconducting qubits
By Chen Wang, C. Axline, Yvonne Y Gao, T. Brecht, Luigi Frunzio, Michel H. Devoret, Robert J. Schoelkopf. 2015
342 citations recorded by the source corpus.
We study the energy relaxation times (T1) of superconducting transmon qubits in 3D cavities as a function of dielectric participation ratios of material surfaces. This surface participation ratio, representing the fraction of electric field energy stored in a dissipative surface layer, is computed by a two-step finite-element simulation and experimentally varied by qubit geometry. With a clean electromagnetic environment and suppressed non-equilibrium quasiparticle density, we find an approximately proportional relation between the transmon relaxation rates and surface participation ratios. These results suggest dielectric dissipation arising from material interfaces is the major limiting factor for the T1 of transmons in 3D circuit quantum electrodynamics architecture. Our analysis also supports the notion of spatial discreteness of surface dielectric dissipation.
Subfields: Artificial Intelligence, Atomic and Molecular Physics, and Optics
View Paper: https://www.semanticscholar.org/paper/be95a09cfa8b3af2a1c4900c2f580dd04a408e34
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In Artificial Intelligence
- Steven M. Girvin
- Alexandre Blais
- Andreas Wallraff
- A. Grimsmo
- A. Somoroff
- N. Grabon
- Long B. Nguyen
- V. Manucharyan
In Atomic and Molecular Physics, and Optics
- Steven M. Girvin
- Alexandre Blais
- Andreas Wallraff
- A. Grimsmo
- A. Somoroff
- N. Grabon
- Long B. Nguyen
- V. Manucharyan
Citations in the corpus
- Circuit quantum electrodynamics (2020, background): “…of internal losses in superconducting resonators at low power are believed to be two-level systems (TLSs) that reside in the bulk dielectric, in the metal substrate, and in the metal-vacuum and substrate-vacuum interfaces where the electric field is large (Sage et al., 2011; Wang et al., 2015).”
- High-Coherence Fluxonium Qubit (2018, methodology): “The former effect is believed to be due to microscopic two-level charge defects residing in the interface oxide layers of a typical thin-film device [10,11].”