CMOS low-noise amplifier design optimization techniques

By Trung‐Kien Nguyen, Chung-Hwan Kim, G. Ihm, Moon-Su Yang, Sang-Gug Lee. IEEE transactions on microwave theory and techniques, 2004

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A 3–10-GHz Low-Power CMOS Low-Noise Amplifier for Ultra-Wideband Communication (2011, background): “Moreover, it requires moderate to large silicon area and introduces a high insertion-loss that degrades the amplifier NF and gain.”
An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system (2005, methodology): “The design principles and the measurement results of the implemented 3.1–5-GHz UWB LNA are described.”
Design of Ultra-Low-Voltage RF Frontends With Complementary Current-Reused Architectures (2007, background): “Assuming that the losses from the matching network are negligible, the conjugate matching conditions are given by [16] (11) (12) (13) (14) In addition to the amplifier gain, the noise figure is also an important design consideration for the impedance matching of the LNA circuits.”
Wideband Common-Gate CMOS LNA Employing Dual Negative Feedback With Simultaneous Noise, Gain, and Bandwidth Optimization (2010, background): “The inductor-degenerated LNA used in conventional wireless receivers can offer simultaneous noise and power match by shifting the optimum noise impedance to the desired value, but only in a narrowband around a single frequency [ 7 ].”