Design of a 1st Generation Neurocomputer
By U. Ramacher, J. Beichter, W. Raab, J. Anlauf, N. Bruls, U. Hachmann, M. Wesseling. 1991
Subfields: Model Architectures, ML Systems & Hardware
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Citations in the corpus
- In-datacenter performance analysis of a tensor processing unit (2017, methodology): “from the Unified Buffer. As reading a large SRAM uses much more power than arithmetic, the matrix unit uses systolic execution to save energy by reducing reads and writes of the Unified Buffer [Kun80][Ram91][Ovt15b]. It relies on data from different directions arriving at cells in an array at regula”
- Programmable Neurocomputing (background): “The most advanced of these systems is the Synapse-1 constructed and sold by Siemens [13].”