Secure Function Evaluation Using an FPGA Overlay Architecture

By Xin Fang, Stratis Ioannidis, Miriam E. Leeser. 2017

23 citations recorded by the source corpus.

Secure Function Evaluation (SFE) has received considerable attention recently due to the massive collection and mining of personal data over the Internet, but large computational costs still render it impractical. In this paper, we leverage hardware acceleration to tackle the scalability and efficiency challenges inherent in SFE. To that end, we propose a generic, reconfigurable implementation of SFE as a coarse-grained FPGA overlay architecture. Contrary to tailored approaches that are tied to the execution of a specific SFE structure, and require full reprogramming of an FPGA with each new execution, our design allows repurposing an FPGA to evaluate different SFE tasks without the need for reprogramming. Our implementation shows orders of magnitude improvement over a software package for evaluating garbled circuits, and demonstrates that the circuit being evaluated can change with almost no overhead.

Subfields: Artificial Intelligence

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Citations in the corpus

HEAX: An Architecture for Computing on Encrypted Data (2019, methodology): “can also be used for the task of privacy-preserving MLaaS. The Garbled Circuits protocol [76] is one of the secure two-party computation protocols for which FPGA-based accelerators have been proposed [43, 32, 44]. However, compared to HE, the communication between parties is signiﬁcantly higher, mak”
HEAX: High-Performance Architecture for Computation on Homomorphically Encrypted Data in the Cloud (2019, methodology): “The Garbled Circuits protocol [76] is one of the secure two-party computation protocols for which FPGA-based accelerators have been proposed [43, 32, 44].”