A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations

By Fuxi Cai, Justin M. Correll, Seung Hwan Lee, Yong Lim, V. Bothra, Zhengya Zhang, M. Flynn, Wei Lu. Nature Electronics, 2019

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A compute-in-memory chip based on resistive random-access memory (2022, neutral): “…bidirectional (forwards and backwards) dataflow requires either dupli-cating power-hungry and area-hungry ADCs at both ends of the RRAM array 11,34 or dedicating a large area to routing both rows and columns of the array to shared data converters 15 ; the recurrent connections require…”
Hardware implementation of memristor-based artificial neural networks (2024, positive): “The MATLAB code employed to train an ANN containing one 64 × 10 Single Layer Perceptron (SLP) ANN — using MNIST images downsized to 8 × 8 — is shown in Supplementary Algorithm 3; the code depicts both the ANN creation and training.”
Three-dimensional memristor circuits as complex neural networks (2020, background): “Emerging non-volatile devices 4,5 , such as memris-tors 6–8 , can directly implement synaptic weights and efficiently carry out resource-hungry matrix operations inside ensemble arrays 9–17 .”