Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs
By M. D. Marchi, D. Sacchetto, S. Frache, Jian Zhang, P. Gaillardon, Yusuf Leblebici, G. D. Micheli. International Electron Devices Meeting, 2012
276 citations recorded by the source corpus.
Subfields: Biomedical Engineering, Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/927a34ab4366104a586e7565d293272502338b0a
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In Biomedical Engineering
In Electrical and Electronic Engineering
Citations in the corpus
- Charge-Plasma Based Process Variation Immune Junctionless Transistor (2014, background): “Similar concept is also explored for MOSFETs [15], [16].”
- Reconfigurable logic and neuromorphic circuits based on electrically tunable two-dimensional homojunctions (2020, background): “10 102 Pstatic = Idd-static × Vdd (4) 103 where Idd-static is the current that flows through the two ETH devices when the inverter 104 is in a steady state.”